The invention relates generally to the field of application specific integrated circuits. In particular, the invention relates to methods of generating application specific integrated circuits using a fixed but configurable hardware architecture.
BACKGROUND OF THE INVENTION
Custom integrated circuits are widely used today in the electronics industry. The demand for custom integrated circuits is rapidly increasing because of a dramatic growth in the demand for highly specific consumer electronics and a trend towards increased product functionality. Also, the use of custom integrated circuits is advantageous because they reduce system complexity and, therefore, lower manufacturing costs, increase reliability and increase system performance.
There are numerous types of custom integrated circuits. One type is programmable logic devices (PLDs) including field programmable gate arrays (FPGAs). FPGAs are designed to be programmed by the end user using special-purpose equipment. Programmable logic devices are, however, undesirable for many applications because they operate at relatively slow speeds, have relatively low capacity, and have relatively high cost per chip.
Another type of custom integrated circuit is application-specific integrated circuits (ASICs) including gate-array based and cell-based ASICs which are often referred to as xe2x80x9csemicustomxe2x80x9d ASICs. Semicustom ASICs are programmed by defining either a) defining the placement and interconnection of a collection of predefined logic cells which are used to create a mask for manufacturing the IC (cell-based) or b) defining the final metal interconnection layers to lay over a predefined pattern of transistors on the silicon (gate-array-based). Semicustom ASICs can achieve high performance and high integration but can be undesirable because they have relatively high design costs, have relatively long design cycles (time it take to transform given functionality into a mask), and relatively low predictability of integrating into an overall electronic system.
Another type of custom integrated circuit is referred to as application-specific standard parts (ASSPs) which are non-programmable integrated circuits that are designed for specific applications. These devices are typically purchased off-the-shelf from integrated circuit suppliers. ASSPs have predetermined architectures and input and output interfaces. They are typically designed for specific products and, therefore, have short product lifetimes.
Yet another type of custom integrated circuit is referred to as a software-only design. This type uses a general purpose processor and a high-level compiler. The end user programs the desired functions with a high-level language. The compiler generates the machine code that instructs the processor to perform the desired functions. Software-only designs typically require general-purpose hardware to perform the desired function. In addition, software only designs have relatively poor performance because the hardware is not optimized to perform the desired functions.
FIG. 1 illustrates a flow chart of a prior art custom integrated circuit design cycle 10. The first step 12 is to design the system at a functional level. A system partitioning step 14 partitions the functional design into a plurality of tasks. A hardware implementation step 16 selects the hardware for the design. A gate level design step 18 configures the logic to implement the hardware design. A netlist generating step 20 produces a netlist of the gate level design. A physical design step 22 determines the geometry of the integrated circuit. A fabrication and manufacturing step 24 generates the custom integrated circuit.
If a general purpose processor (not shown) is used in the custom integrated circuit, additional steps are required. There is a software implementation step 26 where the functional design is coded in software. A hardware/software coverification step 28 verifies the hardware and software implementations. There is also a system integration step 30 that links the hardware and software steps. These steps can add more than 30% to the design cycle.
Today, the custom integrated circuit design cycle 10 typically takes 6-15 months to complete and may cost between one and three million dollars. There are many transformation, analysis and verification steps in the design cycle 10. The design cycle 10 also has potentially time consuming and expensive iterations. Customer modifications or problems occurring during the design cycle may require costly redesign and long delays.
Because of the trend towards increased product functionality in the electronic industry, the complexity of custom integrated circuits is rapidly increasing. The level of skill required to generate custom integrated circuits and the design cycle time is also rapidly increasing. Consequently, prior art methods of generating custom integrated circuits are becoming increasingly inadequate. There currently exists a need for a method of generating application specific integrated circuits that reduces the design cycle time of custom integrated circuits. There also exists a need for a method of generating application specific integrated circuits that allows for modification during the design cycle.
It is therefore a principal object of this invention to greatly reduce the number of steps that it takes to produce an application specific integrated circuit and, therefore, to greatly reduce the design cycle time and the manufacturing cost. It is another object of this invention to provide a method of generating an application specific integrated circuit that easily implements design modifications during the design cycle.
It is another object of this invention to reduce the engineering skill level required to create an application specific integrated circuit. A principal discovery of the present invention is that a custom integrated circuit can be produced by programming a fixed architecture integrated circuit using a high-level object oriented programming language. It is another principal discovery that a custom integrated circuit can be produced by as little as two steps comprising describing the desired functionality of the integrated circuit in an object oriented programming language and compiling the object oriented program onto the fixed programmable architecture.
It is yet another principal discovery that a compiler can be used to perform high level synthesis to map specific functions of an application onto task engines comprised of set data paths in the PSA (programmable system architecture) IC thereby eliminating time intensive analysis of possible data path.
Accordingly, the present invention features a method for generating an application specific integrated circuit that includes providing a software configurable semiconductor integrated circuit having a fixed hardware architecture. The architecture includes a plurality of task engines that executes microtask instructions. The microtask instructions may comprise a Very Long Instruction Word (VLIW) program. The microtask instructions may also be loaded into program memory associated with particular task engines.
A user created high-level language program may be provided that defines the application specific integrated circuit. The high-level language may be an object oriented programming language such as the Java programming language. At least one object oriented class library that performs algorithms, data communications or data manipulations may be provided. The high-level program may be mapped to particular task engines to implement a communication protocol for at least one of an input or an output interface of the fixed hardware architecture.
A high-level language compiler is provided that compiles the high-level language program. The compiler parses the program into a plurality of microtasks that instruct the plurality of task engines to implement the application specific integrated circuit. The program may be parsed into a plurality of threads that are subsequently decomposed into microtasks. The compiler may be optimized to select an optimum task engine for each of the microtasks. For example, the compiler may insert direct memory data references in each of the microtasks. A schedule of multiple microtasks may be statically defined.
The present invention also features a method for generating an application specific integrated circuit. The method includes providing a software configurable semiconductor integrated circuit having a fixed hardware architecture. The hardware architecture includes a plurality of task engines.
A user created high-level language program is provided that defines the application specific integrated circuit. A high-level language compiler is also provided that compiles the high level language program. The compiler parses the program into a plurality of microtasks that instruct the plurality of task engines to implement the application specific integrated circuit.
The present invention also features an apparatus for generating an application specific integrated circuit that includes a semiconductor integrated circuit having a fixed hardware architecture. The hardware architecture includes a plurality of task engines. The plurality of task engines are programmable with a VLIW instruction set that may be unique to each particular task engine. At least one task engine may be included that programs an input and an output interface for accepting data with a communication protocol. The hardware architecture may also include a program memory associated with each of the task engines for storing microtasks for instructing the task engines.
A high-level language compiler compiles a user created high-level language program that defines the application specific integrated circuit. The compiler parses the program into a plurality of microtasks that instruct the plurality of task engines to implement the application specific integrated circuit. The apparatus may also include a software simulator that evaluates particular architectures.